As electronic equipment is reduced in weight, thickness and size, high-density packaging technology in semiconductor packages is developing along with the downsizing and high integration of semiconductor elements.
In the packaging of a semiconductor element, such as an IC chip, a connection between a wiring substrate and the semiconductor element within a package is made by means of wire bonding connection using a gold wire or the like or flip-chip connection using a solder ball or the like.
Wire bonding connection has the advantage of being capable of packaging at low cost if the number of connecting pads of the semiconductor element is small. A wire diameter has to be made smaller, however, with an increase in the number of connecting pads and a decrease in pitch. Accordingly, wire bonding connection has the problem that a yield degrades due to assembly failure, such as wire breakage. In addition, wire bonding connection requires a certain distance to be secured in a connection path between a terminal of the semiconductor element and the wiring substrate. Thus, wire bonding connection is liable to cause degradation in high-speed transmission characteristics.
Flip-chip connection enables high-speed signal transmission, since a connection path between the semiconductor element and the wiring substrate is shorter, compared with a connection path in wire bonding connection. In addition, it is possible to increase the number of connecting terminals since terminals can be provided not only in the periphery of a circuit-formed surface of the semiconductor element but also across the entire range thereof. As the number of connecting pads of the semiconductor element increases and a pitch between connecting pads becomes narrower, however, connection strength decreases with a decrease in the size of a solder bump. Accordingly, flip-chip connection has the problem of being liable to cause connection failure, such as cracks.
In recent years, packaging technology for embedding a semiconductor element in a wiring substrate, i.e., so-called semiconductor element-embedding technology has been proposed as high-density packaging technology for facilitating the further densification and functional upgrading of a semiconductor device.
For example, Patent Literature 1 describes a multilayer printed-wiring substrate in which interlayer insulating films and conductor layers are repetitively formed on the substrate including electronic components built therein, and the electronic components are electrically connected to the conductor layers through vias formed in the interlayer insulating films. In this multilayer printed-wiring substrate, a transition layer for connection with a via of the lowermost interlayer insulating film is formed on an upper portion of each die pad of the electronic components. The patent literature describes that this configuration improves the connectivity of the pad and the via and the reliability of connection therebetween.
Patent Literature 2 discloses a semiconductor device provided with a semiconductor structure (CSP: chip size package) including a semiconductor chip, a rewiring line on this semiconductor chip, a sealing film covering this rewiring line, and a columnar electrode on this rewiring line; a frame-shaped embedding material provided laterally to this semiconductor structure; a sealing film provided between this semiconductor structure and this frame-shaped embedding material; an insulating film covering this semiconductor structure; and an upper layer-side rewiring line provided on this insulating film and connected to the columnar electrode, wherein the semiconductor structure and the frame-shaped embedding material are provided on a base plate.
Patent Literature 3 discloses a semiconductor device in which a plurality of chips is stacked and built in a wiring substrate, and an external terminal is provided on the rear surface side of this wiring substrate.
Patent Literature 4 discloses a multilayer wiring substrate provided with an antenna section in which a plurality of insulated substrates including antenna-composing patterns formed therein is stacked with an intervention of adhesive layers and the antenna-composing patterns are connected to one another by way of feedthrough electrodes, thereby forming an antenna coil; and an electronic component connected to the antenna coil of this antenna section by way of feedthrough electrodes and buried in the adhesive layers.